Data terminals, such as computers, typically use a parallel bus for the transfer of address, data and control information. However, peripheral devices connected to the host computer frequently use a serial data bus to communicate the data. A serial communications card is used to interface between the parallel data format used by the host and the serial data format used by the peripheral device. The serial communications card frequently contains a universal asynchronous receiver/transmitter, such as the National Semiconductor 8250 or the 16450, to perform the conversion between the different data formats. When the UART is receiving data from the peripheral device, such as a modem, it will generate an interrupt each time that a complete character has been received. The host computer must then read this character before the next complete character has been received or the character will be lost. If the serial data rate between the UART and the peripheral device is low, then the host computer will be able to service the interrupt with little or no delay. However, at higher data transfer rates, the host computer may not be able to service the interrupt quickly enough to prevent the loss of the current data character. The National Semiconductor 16550 UART provides a partial solution to this problem in that it contains a first in, first out (FIFO) buffer so that up to 16 characters may be accumulated without servicing before any data character is lost. Therefore, this buffer prevents the loss of received data when the host computer is occasionally too slow. This buffer may be enabled or disabled by an application program by writing to the FIFO enable bit in the UART FIFO register. When both the transmit FIFO and the receive FIFO are enabled, the UART sets bits 6 and 7 in the interrupt identification register, and may set bit 3 (interrupt ID bit 2) in the interrupt identification register and may set bit 7 (error in receiver FIFO) in the line status register. However, for the FIFOs to be used, the application program must enable the FIFO and must not object to the FIFO-related bits in the UART being set. However, most application programs currently available cannot enable the FIFO and, further, regard the setting of the FIFO-related bits as an error condition.
Therefore, there is a need for a method and apparatus for enabling the FIFO registers when the application program is incapable of doing so.
Furthermore, there is a need for a method and apparatus for preventing an existing application program from treating the setting of the FIFO-related bits as an error condition.
Therefore, there is a need for a serial communications card which uses a UART having a FIFO buffer, and which is compatible with programs that accommodate the FIFO feature in the UART, as well as programs which are incapable of accommodating the FIFO feature.